1. Field of the Invention
This invention relates in general to a semiconductor manufacturing method, and more particularly to a self-aligned silicide (salicide) manufacturing method.
2. Description of the Related Art
In accordance with the increase in the level of semiconductor component integration, designed dimensions of components gradually become smaller and smaller, which raises the resistance of the source and drain terminals of a MOS component to a level comparable to the MOS channel. To adjust the sheet resistance of both the drain and the source, as well as to keep a shallow contact surface between the metal and MOS layer intact, a so-called self-aligned silicide (salicide) manufacturing process is employed, and has gradually become a part of the VLSI manufacturing process at line widths of 0.5 .mu.m or below.
Titanium is one of the most commonly used heat resistant metallic materials for using in salicide processing (others include metals such as platinum and cobalt). The conventional manufacturing process includes forming a thin titanium layer above the gate defined silicon chip by a sputtering method, and using a high temperature to make the titanium react with polysilicon layers above the gate and source/drain terminals, thus forming titanium silicide. After the unreacted titanium is removed by a wet etching method, a thin titanium silicide layer on each of the three MOS terminals (gate, source, drain) is left behind. Because the self-aligned silicide manufacturing process can form a low resistance metallic silicide (such as titanium silicide) on the surface of silicon and polysilicon, which is formed without photolithographic processing, the manufacturing process is rather simple, except that the operating conditions for rapid thermal annealing in the silicide processing need to be monitored carefully.
A conventional self-aligned silicide manufacturing method is now described as an example illustrating the manufacturing process. Referring to FIG. 1A, a semiconductor silicon substrate 10 is provided, and a field oxide layer 12, a transistor with a gate made from an oxide layer 14 and a polysilicon gate terminal electrode 16 together with source/drain diffusion regions 20 are formed on the substrate 10. Sidewall spacers 18 are also formed on two sidewalls of the gate.
Then, referring to FIG. 1B, a heat resistant metallic layer 22 (for example, titanium, cobalt or platinum) is formed above the substrate 10 by a DC sputtering method. For this example and in this illustration, a titanium layer 22 is formed.
Finally, referring to FIG. 1C, at a high temperature and using rapid thermal processing, titanium in contact with the gate and source/drain diffusion regions reacts to form thin titanium silicide layers 24 and 26 on the surface of the gate and the source/drain terminals. In other areas, the titanium layer 22 remains unreacted and is removed by a subsequent wet etching method.
For component dimensions having a line width of less than 0.4 .mu.m, using self-aligned titanium silicide has become a necessary part in the processing because the lower sheet resistance and contact resistance provided by the process is very important for achieving high speed/low energy components.
In conventional processing methods, plating a thicker layer of metallic titanium usually can form a better titanium silicide layer accompanied by a better sheet resistance and contact resistance, however the resulting junction depth is shallower which can disadvantageously result in a higher leakage current. Moreover, the high temperature needed in the silicide formation step is difficult to control. Although rapid thermal processing (RTP) techniques have been widely applied in this processing step, the relative newness of RTP, along with other processing factors makes the yield from self-aligned silicide processing still much lower than in conventional processing.